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| Advance Information VT98000 Multifrequency Synthesizer Applications *= Set-top boxes *= MPEG Video clock source General Description The Vaishali VT98000 is a single-chip, integrated multiple Phase Locked Loop (PLL) clock synthesizer. The device uses an analog Phase Locked Loop (PLL) to accept a 27 MHz crystal input to produce multiple outputs. Selection pins are used to provide various outputs. Features *= *= *= *= 24.576 MHz for Firewire IEEE1394 or video digitizer 24.576 MHz / 28.224 MHz for software or hardware modem 27 MHz buffered output clock 6.000MHz buffered output clock *= *= *= *= *= 18.432 MHz for audio processor 2kHz standby clock Zero ppm synthesis error in all clocks (except the 2 kHz standby clock) 5V tolerant inputs 20-pin, 150 mil SSOP (QSOP) Figure 1. Functional Block Diagram VDD1 VDD2 VDD3 VDD4 ROM Table 24.576/ 28.224 MHz X2 Buffer osc 27 MHz Crystal Select 24/28 MHz PLL Multiplier X1 Buffer 24.576 MHz MODE 18.432MHz/ 6.000MHz Divider /PD Buffer Buffer Buffer Buffer 2kHz 27 MHz 27 MHz GND1 GND2 GND3 GND4 GND5 2001-04-17 Vaishali Semiconductor Page 1 www.vaishali.com 1300 White Oaks Road Ste. 200 Campbell CA 95008 MDST-0013-00 Ph. 408.377.6060 Fax 408.377.6063 VT98000 Advance Information Figure 2. Pin Configuration VT98000 Select 24/28MHz X2 X1 VDD1 VDD2 GND1 GND2 24.576MHz MODE 24.576MHz/28.224MHz 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND5 27MHz 27MHz VDD4 VDD3 GND4 GND3 18.432MHz/6.000MHz /PD 2kHz Table 1. Pin Description Name Select 24/28 MHz X2 X1 VDD1 VDD2 GND1 GND2 24.576 MHz MODE 24.576 MHz/ 28.224MHz 2 kHz /PD (1) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18,19 20 Type I(PU) O I P P P P O I(PU) O O I(PU) O P P P P O P Description Select 24.576 MHz or 28.224 MHz output Crystal connection. Connect to a 27 MHz crystal Crystal connection. Connect to a 27 MHz crystal Connect to 3.3V Connect to VDD Connect to ground Connect to ground Clock output, 24.576 MHz Mode control. See Table 2 Clock output, 24.576 MHz or 28.224 MHz Clock output, 2 kHz Powerdown control. When LOW, all clocks are disabled except 2kHz standby clock Clock output, 18.432 MHz or 6.000 MHz Connect to ground Connect to ground Connect to VDD Connect to VDD 27 MHz buffered clock outputs Connect to ground 18.432MHz/6.000MHz GND3 GND4 VDD3 VDD4 27 MHz GND5 Legend: I = Input O = Output P = Power supply connection I(PU) = Input with a 250k ohm pull up Note (1). All disabled clock outputs are tristated (high impedance). 2001-04-17 Vaishali Semiconductor Page 2 www.vaishali.com 1300 White Oaks Road, Ste. 200 Campbell MDST-0013-00 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 VT98000 Advance Information (1,2) Table 2. Mode Control and Frequency Selection Table (/PD = HIGH) Control Pin 9 Mode 0 0 1 1 (3) Outputs Pin 10 (24.576 MHz / 28.224 MHz) High Impedance Pin 13 (18.43 MHz / 6 MHz) 18.432 MHz Pin 1 (Select 24/28MHz). 0 1 0 1 24.576 MHz 6 MHz 28.224 MHz Notes: 1. 27MHz (Pins 18 &19) and 24.576 MHz (Pin 8) are active, unless /PD = LOW 2. 2 kHz standby clock is always active, independent of /PD logic state 3. 0 = Low, 1 = HIGH Table 3. Recommended Crystal Specification Frequency accuracy is directly proportional to the capacitive load (CL) of the crystal. Parameter Frequency at CL, FL Total accuracy: includes initial accuracy @ 25C, aging, and temperature drift (25C to 70C) Load Capacitance CL C1 C0 ESR Definition Defines the series resonant frequency at CL Maximum deviation from nominal frequency @ 25C, taking in to account aging, and temperature drift Capacitive load for nominal frequency FL Motional capacitance of the crystal Shunt capacitance of the crystal Equivalent Series Resistance of the crystal Min Typ 27.000 Max Units MHz 40 ppm 20 TBD 7 40 pf pf pf ohms Table 4. Operating Conditions Parameter Power Supply Voltage, VDD Input High Voltage, VIH Input Low Voltage, VIL Operating Temperature,TA 0 25 Conditions Min 3.0 2.0 Typ 3.3 Max 3.6 VDD 0.8 70 Units V V V C Table 5. Electrical Characteristics Parameter Output voltage high IOH = -8 mA Output voltage low IOL = 8 mA Maximum input capacitance (X1,X2) Power consumption (operating) Power consumption (powerdown) Symbol VOH VOL Cin Idd1 Idd2 Min 2.7 Typ Max 0.4 3 Units V V pF mA mA 2001-04-17 Vaishali Semiconductor Page 3 www.vaishali.com 1300 White Oaks Road, Ste. 200 Campbell MDST-0013-00 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 VT98000 Advance Information Table 6. Phase Noise Requirements (Crystal phase noise must be less than -130 dBc/Hz @ 10kHz) Parameter 27 MHz 24.576 MHz 24.576/28.224 MHz 18.432/6.000 MHz Symbol Min -120 -100 -100 -100 Typ Max Units dBc/Hz @ 10 kHz dBc/Hz @ 10 kHz dBc/Hz @ 10 kHz dBc/Hz @ 10 kHz Table 7. Output Accuracies (Excluding crystal accuracy) Parameter 24.576/28.224 MHz 2kHz 18.432/6.000 MHz 27 MHz Symbol Min Typ Max 0 50 0 0 Units ppm % ppm ppm Table 8 AC Characteristics All @Cload = 20 pF, VDD = 3.0V to 3.6V Parameter Duty Cycle @ VDD/2 Rise time ( measured between 0.8V and 2.0V) Fall time ( measured between 0.8V and 2.0V) PLL lock time Time to clock outputs after VDD is available Symbol Tr Tf Tlock Tst Min 1 1 Typ Max 45/55 2.5 2.5 Units % ns ns ms 50 ms Ordering Information Part Number VT98000Q VT98000QX Marking VT98000Q VT98000Q Shipping/Packaging Tubes Tape & Reel No. of Pins 20 20 Package QSOP QSOP Temperature 0C to +70C 0C to +70C 2001-04-17 Vaishali Semiconductor Page 4 www.vaishali.com 1300 White Oaks Road, Ste. 200 Campbell MDST-0013-00 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 |
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